In these applications, the circuits are generally produced in CMOS (complementary metal oxide semiconductor) technology which allows lower consumption than other technologies.
To switch from an active mode to a standby mode, as seen in FIG. 1, an MOS power transistor TP interposed in series between one of the supply terminals A or M of the integrated circuit and the active part of the circuit (CA) is in general provided in the integrated circuit. This transistor is controlled by a mode control circuit CGM which establishes on the gate of the transistor one voltage or another voltage depending on whether the integrated circuit is in active mode or in standby mode. The function of this power transistor is twofold:                in active mode, it is made highly conducting and lets through all the current needed for the active circuit, with a minimal voltage drop and therefore without needless power consumption;        in standby mode, it is blocked so as to interrupt the current from the supply voltage to the rest of the integrated circuit.        
The power transistor must therefore meet several constraints: sufficiently high current in the on-state; very low voltage drop in the on-state; very low leakage currents in the off-state; and finally, if possible, dimensions as small as possible in order to reduce the footprint on the silicon of the integrated circuit.
Various types of power transistors attempting to meet this set of constraints have already been proposed in the prior art. Examples thereof are found notably in the following published documents:                “1-V Power Supply High Speed Digital Circuit Technology with Multithreshold-voltage CMOS”, IEEE Journal of Solid State Circuits, Vol. 30, pp 847-854, August 1995 by S. Mutoh et al.;        “Boosted Gate OS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration”, Custom Integrated Circuits Conference, pp. 409-412, May 2000 by T. Inukai et al.; and        “A super Cut-Off CMOS (SCCMOS) Scheme for 0.5 V Supply Voltage with Picoampere Stand-by Current”, IEEE Journal of Solid State Circuits, Vol. 35 No 10, pp 1498-1501, October 2000 by H. Kawaguchi et al.        
In the latter document, a power transistor having a low threshold voltage is used that delivers a high current in the on-state, the leakage current of which is reduced by reverse overbiasing the gate in standby mode. The term “reverse overbias” is understood to mean a bias at a voltage lower than the most negative terminal of the supply voltage for an nMOS transistor or higher than the most positive supply voltage for a pMOS transistor.
The type of power transistor of the last-mentioned document (SCCMOS) is that providing the best compromise between area occupied (for a given current in the on-state) and leakage current in the off-state.
It should be noted that the leakage current, which is firstly due to the conduction current ISTH between source and drain (threshold current ISTH), decreases exponentially as the gate is biased more negatively (for an nMOS transistor). It may become extremely low, but other phenomena cause other leakage currents that may increase with the overbias voltage.
Reverse gate overbias control circuits have therefore already been proposed which establish a reverse overbias voltage which is neither too low nor too high. These control circuits are sophisticated—they include current sources, comparators, voltage step-up charge pumps, etc. They require themselves energy to operate, which goes counter to reducing consumption in the quiescent state. Such circuits have for example been proposed in the following publication: “Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability”, by A. Valentian and E. Beigne, published in IEEE Journal of Solid-State Circuits, Volume 43, No. 7, July 2008, pages 1688-1698.
It should also be noted that gate forward bias control circuits have already been proposed in the prior art using charge pumps operating at a variable frequency—see the U.S. Pat. No. 5,258,662.
One aim of the invention is to propose a gate reverse overbias control circuit having a minimal energy consumption.